6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS-Reference-Cited by-同舟云学术

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6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS

Published:2020-02 Issue: Volume: Page:
ISSN:
Container-title:2020 IEEE International Solid- State Circuits Conference - (ISSCC)
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Author:

Park Kwanseo,Shim Minkyo,Ko Han-Gon,Jeong Deog-Kyoon

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9046640/9062887/09063010.pdf?arnumber=9063010

Cited by 24 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Sub-Baud-Rate Wireline Receiver With One-Tap DFE;IEEE Journal of Solid-State Circuits;2024

2. A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology;2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS);2023-10-16

3. A Sub-Sampling Phase Detector for Low-Power PAM4 Clock Recovery Circuit;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06

4. A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-07

5. A 6.0–11.0 Gb/s Reference-Less Sub-Baud-Rate Linear CDR With Wide-Range Frequency Acquisition Technique;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-02

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