6.8 A 36Gb/s Adaptive Baud-Rate CDR with CTLE and 1-Tap DFE in 28nm CMOS-Reference-Cited by-同舟云学术

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6.8 A 36Gb/s Adaptive Baud-Rate CDR with CTLE and 1-Tap DFE in 28nm CMOS

Published:2019-02 Issue: Volume: Page:
ISSN:
Container-title:2019 IEEE International Solid- State Circuits Conference - (ISSCC)
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Author:

Yoo Danny,Bagherbeik Mohammad,Rahman Wahid,Sheikholeslami Ali,Tamura Hirotaka,Shibasaki Takayuki

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8656625/8662285/08662379.pdf?arnumber=8662379

Cited by 16 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 0.45 pJ/b 24 Gb/s NRZ Receiver Data-Path Using Half-Baud-Rate Duobinary Sampling;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-09

2. A 20-Gb/s Jitter-Tolerance-Enhanced Baud-Rate CDR Circuitwith One-Tap DFE;2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA);2024-04-22

3. A Sub-Baud-Rate Wireline Receiver With One-Tap DFE;IEEE Journal of Solid-State Circuits;2024

4. A 1.1-pJ/b 8-to-16-Gb/s Receiver With Stochastic CTLE Adaptation;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-02

5. A 12.93–16 Gb/s Reference-Less Baud-Rate CDR Circuit With One-Tap DFE and Semirotational Frequency Detection;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023

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