A 112 Gb/s -8.2 dBm Sensitivity 4-PAM Linear TIA in 16nm CMOS with Co-Packaged Photodiodes
Author:
Affiliation:
1. University of Toronto,Toronto,ON,Canada
2. Huawei Technologies,Toronto,ON,Canada
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9772767/9772730/09772827.pdf?arnumber=9772827
Reference6 articles.
1. A 53-Gbit/s Optical Receiver Frontend With 0.65 pJ/bit in 28-nm Bulk-CMOS
2. A Low-Noise Design Technique for High-Speed CMOS Optical Receivers
3. A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS
4. 29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET
5. A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s/$\lambda$ PAM-4 Optical Links
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