A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS-Reference-Cited by-同舟云学术

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A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS

Published:2018-09 Issue: Volume: Page:
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Container-title:ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)
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Author:

Li Hao,Balamurugan Ganesh,Jaussi James,Casper Bryan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8476980/8494227/08494285.pdf?arnumber=8494285

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