Low-power and small-area 4-ch 25-Gb/s transimpedance amplifiers in 65-nm CMOS process-Reference-Cited by-同舟云学术

Low-power and small-area 4-ch 25-Gb/s transimpedance amplifiers in 65-nm CMOS process

Published:2023-09-25 Issue:18 Volume:20 Page:20230339-20230339
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Takahashi Yasuhiro¹,Ito Daisuke¹,Nakamura Makoto¹,Tsuchiya Akira²,Inoue Toshiyuki²,Kishine Keiji²

Affiliation:

1. Faculty of Engineering, Gifu University

2. School of Engineering, The University of Shiga Prefecture

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/20/18/20_20.20230339/_pdf

Reference33 articles.

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2. [2] “Co-packaged optics collaboration,” (2021) http://www.copackagedoptics.com (accessed on 10 Feb. 2023).

3. [3] F. Koyama: “High-speed VCSEL photonics for datacenter networks,” Invited Lecture Notes of 2022 URSI-Japan Radio Science Meeting (JRSM 2022) (2022) http://www.ursi.jp/content/files/JRSM2022/ComD_Invited_Fumio_Koyama_URSI-JRSM-2022.pdf (accessed on 11 Feb. 2023).

4. [4] C. Minkenberg, et al.: “Co-packaged datacenter optics: Opportunities and challenges,” IET Optoelectronics 15 (2021) 77 (DOI: 10.1049/ote2.12020).

5. [5] S.-M. Park and H.-J. Yoo: “1.25-Gb/s regulated cascode CMOS transimpedance amplifier for Gigabit Ethernet applications,” IEEE J. Solid-State Circuits 39 (2004) 112 (DOI: 10.1109/JSSC.2003.820884).

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