A 2-GHz Dual-Path Sub-Sampling PLL with Ring VCO Phase Noise Suppression
Author:
Affiliation:
1. Nanyang Technological University,Singapore
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9772767/9772730/09772813.pdf?arnumber=9772813
Reference6 articles.
1. A Low-Jitter Ring-Oscillator Phase-Locked Loop Using Feedforward Noise Cancellation With a Sub-Sampling Phase Detector
2. A 4.2 us-settling time 3rd-order 2.1 GHz phase-noise rejection PLL using a cascaded time-amplified clock-skew sub-sampling DLL;huang;ISSCC,2016
3. A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by $N ^{2}$
4. 25.6 A 5.25GHz Subsampling PLL with a VCO-Phase-Noise Suppression Technique
5. A Spur-and-Phase-Noise-Filtering Technique for Inductor-Less Fractional-N Injection-Locked PLLs
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2. A High-Linearity 19 GHz LC-Based VCO for PVT Compensation;2024 IEEE 7th Advanced Information Technology, Electronic and Automation Control Conference (IAEAC);2024-03-15
3. A 20.8-23.2GHz sub-sampling PLL with transformer-coupled VCO feedback loop achieving -47.05dBc reference spur and -245.9dB FOM in 40nm CMOS technology;IEICE Electronics Express;2023-10-25
4. A Fully Synthesizable DPLL with Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation Path;ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC);2023-09-11
5. A 6-to-7.5-GHz 54-fsrms Jitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction;IEEE Transactions on Circuits and Systems I: Regular Papers;2022-12
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