A Spur-and-Phase-Noise-Filtering Technique for Inductor-Less Fractional-N Injection-Locked PLLs-Reference-Cited by-同舟云学术

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A Spur-and-Phase-Noise-Filtering Technique for Inductor-Less Fractional-N Injection-Locked PLLs

Published:2017-08 Issue:8 Volume:52 Page:2128-2140
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Li Alvin^ORCID,Chao Yue,Chen Xuan,Wu Liang^ORCID,Luong Howard C.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/7987836/07904650.pdf?arnumber=7904650

Cited by 28 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Low Mismatch Current Charge Pump Applied to Phase-Locked Loops;Micromachines;2024-07-14

2. A Simplified Gm − C Filter Technique for Reference Spur Reduction in Phase-Locked Loop;Journal of Low Power Electronics and Applications;2024-03-20

3. A Dual-Path Subsampling PLL With Ring VCO Phase Noise Suppression;IEEE Transactions on Microwave Theory and Techniques;2024-01

4. Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration;IEEE Journal of Solid-State Circuits;2024-01

5. A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction;IEEE Open Journal of Circuits and Systems;2024

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