A Low-Jitter Ring-Oscillator Phase-Locked Loop Using Feedforward Noise Cancellation With a Sub-Sampling Phase Detector-Reference-Cited by-同舟云学术

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A Low-Jitter Ring-Oscillator Phase-Locked Loop Using Feedforward Noise Cancellation With a Sub-Sampling Phase Detector

Published:2018-03 Issue:3 Volume:53 Page:703-714
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Nagam Shravan S.^ORCID,Kinget Peter R.^ORCID

Funder

Semiconductor Research Corporation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/8295182/08271868.pdf?arnumber=8271868

Cited by 38 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. 7.4 A 0.027mm² 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fs_rms Jitter and -74.2dBc Reference Spur;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18

2. A 14 GHz Integer-N Sub-Sampling PLL With RMS-Jitter of 85.4 fs Occupying an Ultra Low Area of 0.0918 mm²;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-02

3. A 2.4-GHz ring-VCO-based time-to-voltage conversion PLL achieving low-jitter and low-spur performance;Microelectronics Journal;2024-01

4. A Dual-Path Subsampling PLL With Ring VCO Phase Noise Suppression;IEEE Transactions on Microwave Theory and Techniques;2024-01

5. An Injection-Locked and Sub-Sampling Clock Multiplier With a Two-Step SC DAC Achieving 2.67% Jitter Variation;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024

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