A 20.8-23.2GHz sub-sampling PLL with transformer-coupled VCO feedback loop achieving -47.05dBc reference spur and -245.9dB FOM in 40nm CMOS technology-Reference-Cited by-同舟云学术

A 20.8-23.2GHz sub-sampling PLL with transformer-coupled VCO feedback loop achieving -47.05dBc reference spur and -245.9dB FOM in 40nm CMOS technology

Published:2023-10-25 Issue:20 Volume:20 Page:20230385-20230385
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Zhang Zhichao¹,Zheng Wenjie¹,Xia Xinlin¹,Wang Yanjie¹

Affiliation:

1. School of Electronic and Information Engineering, South China University of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/20/20/20_20.20230385/_pdf

Reference30 articles.

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4. [4] V. Szortyka, et al.: “A 42mW 200fs-jitter 60GHz sub-sampling PLL in 40nm CMOS,” IEEE J. Solid-State Circuits 50 (2015) 2025 (DOI: 10.1109/JSSC.2015.2442998).

5. [5] Y. Dong, et al.: “A 2-GHz dual-path sub-sampling PLL with ring VCO phase noise suppression,” IEEE Custom Integrated Circuits Conference (CICC) (2022) 1 (DOI: 10.1109/CICC53496.2022.9772813).