Extended Methodology to Determine SRAM Write Margin in Resistance-Dominated Technology Node

Author:

Liu Hsiao-Hsuan1ORCID,Salahuddin Shairfe M.1ORCID,Abdi Dawit1,Chen Rongmei1ORCID,Weckx Pieter1ORCID,Matagne Philippe1ORCID,Catthoor Francky1

Affiliation:

1. IMEC, Leuven, Belgium

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

2. CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark;IEEE Transactions on Electron Devices;2023-10

3. Electromigration-aware design technology co-optimization for SRAM in advanced technology nodes;2023 Design, Automation & Test in Europe Conference & Exhibition (DATE);2023-04

4. CFET SRAM DTCO, Interconnect Guideline, and Benchmark for CMOS Scaling;IEEE Transactions on Electron Devices;2023-03

5. Graphene-Based Interconnect Exploration for Large SRAM Caches for Ultrascaled Technology Nodes;IEEE Transactions on Electron Devices;2023-01

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