Electromigration-aware design technology co-optimization for SRAM in advanced technology nodes
Author:
Affiliation:
1. Karlsruhe Institute of Technology (KIT),Karlsruhe,Germany
2. IMEC vzw,Leuven,Belgium
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10136870/10136706/10137008.pdf?arnumber=10137008
Reference20 articles.
1. Electromigration recovery modeling and analysis under time-dependent current and temperature stressing
2. Electromigration failure of circuit interconnects
3. Extended Methodology to Determine SRAM Write Margin in Resistance-Dominated Technology Node
4. Electromigration—A brief survey and some recent results
5. Yield and speed optimization of a latch-type voltage sense amplifier
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1. Addressing the Combined Effect of Transistor and Interconnect Aging in SRAM towards Silicon Lifecycle Management;2024 IEEE 42nd VLSI Test Symposium (VTS);2024-04-22
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