SRAM dynamic stability: Theory, variability and analysis
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx5/4670335/4681527/04681601.pdf?arnumber=4681601
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Stochastic Nonlinear Dynamical Modelling of SRAM Bitcells in Retention Mode;2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM);2024-03-03
2. Variability-Aware Noise-Induced Dynamic Instability of Ultra-Low-Voltage SRAM Bitcells;2024 IEEE 15th Latin America Symposium on Circuits and Systems (LASCAS);2024-02-27
3. A Timing Yield Model for SRAM Cells at Sub/Near-Threshold Voltages Based on a Compact Drain Current Model;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-04
4. Extended Methodology to Determine SRAM Write Margin in Resistance-Dominated Technology Node;IEEE Transactions on Electron Devices;2022-06
5. Comparison of SRAM Cell Layout Topologies to Estimate Improvement in SER Robustness in 28FDSOI and 40 nm Technologies;Communications in Computer and Information Science;2017
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