A 25-Gb/s CDR in 90-nm CMOS for High-Density Interconnects-Reference-Cited by-同舟云学术

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A 25-Gb/s CDR in 90-nm CMOS for High-Density Interconnects

Published:2006-12 Issue:12 Volume:41 Page:2921-2929
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Kromer Christian,Sialm Gion,Menolfi Christian,Schmatz Martin,Ellinger Frank,Jackel Heinz

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/4014593/04014618.pdf?arnumber=4014618

Cited by 46 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Phase Interpolator-Based Clock and Data Recovery With Jitter Optimization;IEEE Open Journal of Circuits and Systems;2023

2. A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector;2022 IEEE Nordic Circuits and Systems Conference (NorCAS);2022-10-25

3. A 12.5Gbps PI-based Quarter-Rate Clock and Data Recovery Circuit with an Adaptive filter of JESD204B Standard;2021 6th International Conference on Integrated Circuits and Microsystems (ICICM);2021-10-22

4. A High-linearity Phase Interpolator for 12.5Gbps Clock and Data Recovery Circuit of JESD204B Standard;2021 IEEE 6th International Conference on Signal and Image Processing (ICSIP);2021-10-22

5. High-speed Clock and Data Recovery System with Segmented Slew-rate Control Circuit for High-linearity in 65 nm CMOS Process;JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE;2021-06-30

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