Author:
Nii K.,Tsukamoto Y.,Yoshizawa T.,Imaoka S.,Yamagami Y.,Suzuki T.,Shibayama A.,Makino H.,Iwade S.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Cited by
45 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Optimization of the aspect ratio to enhance the power and noise-margin of a standard 6T(S6T)-SRAM cell;2022 Fourth International Conference on Emerging Research in Electronics, Computer Science and Technology (ICERECT);2022-12-26
2. Backgrounds;Processing-in-Memory for AI;2022-07-10
3. Optimization of 1KByte 6T SRAM using block partitioning method and gated Vdd concept;AIP Conference Proceedings;2019
4. Memories for NTC;Near Threshold Computing;2016
5. Device circuit co-design to reduce gate leakage current in VLSI logic circuits in nano regime;International Journal of Numerical Modelling: Electronic Networks, Devices and Fields;2015-09-04