Optimization of 1KByte 6T SRAM using block partitioning method and gated Vdd concept
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http://aip.scitation.org/doi/pdf/10.1063/1.5100399
Reference20 articles.
1. A Low-Power SRAM Using Bit-Line Charge-Recycling for Read and Write Operations
2. Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM
3. Kumkum Verma, Sanjay Kumar Jaiswal and Mohammad Ayoub Khan “Design of a High Performance and Low Power 1Kb 6T SRAM using Bank Partitioning Method”, International Conference on Multimedia, Signal Processing and Communication Technologies, (2011).
4. Anie Jain, Shyam Akashe “Optimization of low power 7T SRAM cell in 45nm technology”, Second International conference on Advanced Computing &Communication Technologies, (2012).
5. Stefan Cosemans, Student Member, IEEE, WimDehaene, Senior Member, IEEE, and FranckyCatthoor, Fellow, IEEE “A Low-Power Embedded SRAM for Wireless Applications”, Journal of solid-state circuits, 42, no. 7, (2007).
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