1. Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors;Ghani;Tech Dig VLSI Sym,2000
2. Impact of gate direct tunneling current on circuit performance: a simulation study;Choi;IEEE Trans Electron Devices,2001
3. International Technology Roadmap for Semiconductors http://public.itrs.net/Files /2001 ITRS /Home.html 2001
4. CMOS design near the limits of scaling;Taur;IBM JR&D,2002
5. High performace low-power CMOS circuits using multiple channel length and multiple oxide thickness;Sirisantana;Proc of IEEE ICCD,2000