A 90-nm FPGA I/O buffer design with 1.6-Gb/s data rate for source-synchronous system and 300-MHz clock rate for external memory interface-Reference-Cited by-同舟云学术

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A 90-nm FPGA I/O buffer design with 1.6-Gb/s data rate for source-synchronous system and 300-MHz clock rate for external memory interface

Published:2005-09 Issue:9 Volume:40 Page:1829-1838
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Tyhach J.,Wang B.,Sung C.,Huang J.,Nguyen K.,Xiaobao Wang ,Yan Chong ,Pan P.,Kim H.,Rangan G.,Tzung-Chin Chang ,Tan J.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/32231/01501981.pdf?arnumber=1501981

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