A Study on Parallel Test Approach for the Flash Burn-in Experiment in Laboratory

Abstract

Abstract With the increasing number of lab burn-in samples, this paper proposes a parallel test approach for the problem that the single-device test board cannot meet the requirements of the JEDEC standard for the large number of samples with high efficiency. The designed FPGA control board independently separates 4 control SCAN signals, different SCAN chips perform read operations in sequence, and complete the operation in parallel. The experimental results show that, compared with the single-device test board, the MT test board can test 80 chips at the same time, which meets the requirements of the JEDEC standard, and reduces the requirement for hardware resources in the burn-in test, and improves test efficiency.