A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM-4 Receiver With a Jitter Compensation CDR-Reference-Cited by-同舟云学术

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A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM-4 Receiver With a Jitter Compensation CDR

Published:2024-02 Issue:2 Volume:59 Page:449-463
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Wang Li¹^ORCID,Zhang Zhao²^ORCID,Wang Can³^ORCID,Azmat Rehan¹,Shi Weimin⁴,Yue C. Patrick¹^ORCID

Affiliation:

1. Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Hong Kong, SAR, China

2. Chinese Academy of Sciences, Institute of Semiconductors, Beijing, China

3. Department of Electrical Engineering, Stanford University, Stanford, CA, USA

4. School of Microelectronics and Communication Engineering, Chongqing University, Chongqing, China

Funder

Research and Development Program in Key Areas of Guangdong Province

General Research Fund of Hong Kong

Areas of Excellence Scheme of Hong Kong

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/10416291/10244204.pdf?arnumber=10244204

Reference39 articles.

1. 23.2 A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme

2. 17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs

3. Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell

4. 3.4 A 40/50/100Gb/s PAM-4 Ethernet transceiver in 28nm CMOS

5. PCI Express® 6.0 Specification at 64.0 GT/s with PAM-4 signaling: a low latency, high bandwidth, high reliability and cost-effective interconnect

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