PCI Express® 6.0 Specification at 64.0 GT/s with PAM-4 signaling: a low latency, high bandwidth, high reliability and cost-effective interconnect

Author:

Sharma Debendra Das

Publisher

IEEE

Cited by 16 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. AttAcc! Unleashing the Power of PIM for Batched Transformer-based Generative Model Inference;Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2;2024-04-27

2. ASADI: Accelerating Sparse Attention Using Diagonal-based In-Situ Computing;2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2024-03-02

3. A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM-4 Receiver With a Jitter Compensation CDR;IEEE Journal of Solid-State Circuits;2024-02

4. Efficient Intra-Rack Resource Disaggregation for HPC Using Co-Packaged DWDM Photonics;2023 IEEE International Conference on Cluster Computing (CLUSTER);2023-10-31

5. Precursor ISI Cancellation Sliding-Block DFE for High-Speed Wireline Receivers;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-10

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