Precursor ISI Cancellation Sliding-Block DFE for High-Speed Wireline Receivers-Reference-Cited by-同舟云学术

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Precursor ISI Cancellation Sliding-Block DFE for High-Speed Wireline Receivers

Published:2023-10 Issue:10 Volume:70 Page:4169-4182
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Kim Kunmo¹^ORCID,Moon Suhong²^ORCID,Han Jaeduk³^ORCID,Alon Elad⁴,Niknejad Ali M.¹^ORCID

Affiliation:

1. Berkeley Wireless Resesarch Center, University of California at Berkeley, Berkeley, CA, USA

2. Berkeley AI Research (BAIR), University of California at Berkeley, Berkeley, CA, USA

3. Department of Electronic Engineering, Hanyang University, Seoul, South Korea

4. Blue Cheetah Analog Design, Sunnyvale, CA, USA

Funder

ComSenTer, a research center part of the Semiconductor Research Corporation (SRC) Program Joint University Microelectronics Program

Doctoral Fellowship of Korea Foundation of Advanced Studies

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Link

http://xplorestaging.ieee.org/ielx7/8919/10268488/10210068.pdf?arnumber=10210068

Reference37 articles.

1. 6.4 A 180mW 56Gb/s DSP-Based Transceiver for High Density IOs in Data Center Switches in 7nm FinFET Technology

2. A comparative study of equalization schemes for 112G PAM4 links;lu;Proc DesignCon,2019

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-Based Wireline Transceivers;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

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