A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS-Reference-Cited by-同舟云学术

A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS

Published:2022-05 Issue:5 Volume:57 Page:1527-1541
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Chun Yusang¹,Megahed Mohamed²^ORCID,Ramachandran Ashwin³^ORCID,Anand Tejasvi²^ORCID

Affiliation:

1. MediaTek USA Inc, Irvine, CA, USA

2. Department of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR, USA

3. Texas Instruments, Santa Clara, CA, USA

Funder

Intel

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9761850/09707488.pdf?arnumber=9707488

Reference49 articles.

1. A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS

2. Power Optimized ADC-Based Serial Link Receiver

3. Equalization for Electrical Links: Current Design Techniques and Future Directions

4. A 56 Gb/s 6 mW 300 $\mu{\mathrm{ m}}^{2}$ inverter-based CTLE for short-reach PAM2 applications in 16 nm CMOS;zheng;Proc IEEE Custom Integr Circuits Conf (CICC),2018

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