Equalization for Electrical Links: Current Design Techniques and Future Directions-Reference-Cited by-同舟云学术

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Equalization for Electrical Links: Current Design Techniques and Future Directions

Published:2015 Issue:4 Volume:7 Page:23-31
ISSN:1943-0582
Container-title:IEEE Solid-State Circuits Magazine
language:
Short-container-title:IEEE Solid-State Circuits Mag.

Author:

Bulzacchelli John F.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4563670/7336635/07336645.pdf?arnumber=7336645

Cited by 27 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Novel 2.7 pJ/bit, Low Supply, Power Efficient, Wide-Range 2.5-6 Gb/s Transmitter for 4-Channel High-Speed Serial Transmit Port (HSSTP) in 28nm FD-SOI Technology;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. 41.6 Gb/s High-Depth Pre-Interleaver for DFE Error Propagation in 65 nm CMOS Technology;Electronics;2023-09-16

3. A 0.8-6Gb/s wireline receiver based on the spectrum-balancing equalizer and semi-digital dual loop CDR;IEICE Electronics Express;2023-05-25

4. A low-power 1 Gb/s line driver with configurable pre-emphasis for lossy transmission lines;Journal of Instrumentation;2023-04-01

5. GMSL: Gigabit Multimedia Serial Link – An Introduction;Handbook of Visual Display Technology;2023

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