An iPWM Line-Coding-Based Wireline Transceiver With Clock -Domain Encoding for Compensating Up To 27-dB Loss While Operating at 0.5-to-0.9 V and 3-to-16 Gb/s in 65-nm CMOS-Reference-Cited by-同舟云学术

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An iPWM Line-Coding-Based Wireline Transceiver With Clock -Domain Encoding for Compensating Up To 27-dB Loss While Operating at 0.5-to-0.9 V and 3-to-16 Gb/s in 65-nm CMOS

Published:2020-07 Issue:7 Volume:55 Page:1946-1959
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Ramachandran Ashwin,Chun Yusang^ORCID,Megahed Mohamed^ORCID,Anand Tejasvi^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9127212/09013068.pdf?arnumber=9013068

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based Time-Domain ZQ Calibration for Memory Interfaces;IEEE Journal of Solid-State Circuits;2024-09

2. A 25-Gb/s Single-Ended PAM-4 Transmitter With iPWM-Based FFE and RLM-Matched Voltage-Mode Driver for High-Speed Memory Interfaces;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

3. A 0.85-pJ/b 16-Gb/s/Pin Single-Ended Transmitter With Integrated Voltage Modulation for Low-Power Memory Interfaces;IEEE Journal of Solid-State Circuits;2023-09

4. A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS;IEEE Journal of Solid-State Circuits;2022-05

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