A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based Time-Domain ZQ Calibration for Memory Interfaces-Reference-Cited by-同舟云学术

A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based Time-Domain ZQ Calibration for Memory Interfaces

Published:2024-09 Issue:9 Volume:59 Page:2971-2982
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Yun Jaekwang¹^ORCID,Lee Sangyoon²^ORCID,Kim Jaewook¹,Chae Joo-Hyung³^ORCID,Kim Suhwan¹^ORCID,Jeong Yong-Un⁴^ORCID

Affiliation:

1. Department of Electrical and Computer Engineering and the Inter-University Semiconductor Research Center (ISRC), Seoul National University, Seoul, South Korea

2. Department of Electrical and Computer Engineering, Seoul National University, Seoul, South Korea

3. Department of Electronics and Communications Engineering, Kwangwoon University, Seoul, South Korea

4. Department of Semiconductor Systems Engineering, Sejong University, Seoul, South Korea

Funder

Institute of Information and Communications Technology Planning and Evaluation (IITP) grant funded by the Ministry of Science and ICT

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/4/10648889/10479183.pdf?arnumber=10479183

Reference27 articles.

1. A 10 Gb/s/pin Single-Ended Transmitter With Reflection-Aided Duobinary Modulation for Dual-Rank Mobile Memory Interfaces

2. Data-Dependent Selection of Amplitude and Phase Equalization in a Quarter-Rate Transmitter for Memory Interfaces

3. A 10.4-Gb/s 1-Tap Decision Feedback Equalizer With Different Pull-Up and Pull-Down Tap Weights for Asymmetric Memory Interfaces

4. A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration

5. 23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme