An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices-Reference-Cited by-同舟云学术

An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices

Published:2024-01 Issue:1 Volume:59 Page:219-230
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

You De-Qi¹^ORCID,Chiu Yen-Cheng¹,Khwa Win-San²,Li Chung-Yuan¹,Hsieh Fang-Ling¹,Chien Yu-An¹,Lo Chung-Chuan¹,Liu Ren-Shuo¹^ORCID,Hsieh Chi-Cheng¹^ORCID,Tang Kea-Tiong¹^ORCID,Chih Yu-Der²,Chang Tsung-Yung Jonathan²,Chang Meng-Fan¹^ORCID

Affiliation:

1. Department of Electrical Engineering, National Tsing Hua University (NTHU), Hsinchu, Taiwan

2. Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan

Funder

Taiwan Semiconductor Manufacturing Company (TSMC)-Joint Developed Project

National Science and Technology Council (NSTC) of Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/10375801/10292992.pdf?arnumber=10292992

Reference40 articles.

1. Challenges and Trends of SRAM-Based Computing-In-Memory for AI Edge Devices

2. Challenges and Trends of Nonvolatile In-Memory-Computation Circuits for AI Edge Devices

3. A 5-nm 254-TOPS/W 221-TOPS/mm² Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations

4. A 1.041-Mb/mm² 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications

5. 16.4 An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications

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1. An 8b-Precison 16-Kb FDSOI 8T SRAM CIM macro based on time-domain for energy-efficient edge AI devices;Microelectronics Journal;2024-09

2. STT-MRAM-based Near-Memory Computing Architecture with Read Scheme and Dataflow Co-Design for High-Throughput and Energy-Efficiency;Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design;2024-08-05