STT-MRAM-based Near-Memory Computing Architecture with Read Scheme and Dataflow Co-Design for High-Throughput and Energy-Efficiency-Reference-Cited by-同舟云学术

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STT-MRAM-based Near-Memory Computing Architecture with Read Scheme and Dataflow Co-Design for High-Throughput and Energy-Efficiency

Published:2024-08-05 Issue: Volume: Page:1-6
ISSN:
Container-title:Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design
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Author:

Jang Yunho¹^ORCID,Kim Yeseul¹^ORCID,Park Jongsun²^ORCID

Affiliation:

1. Korea University, Seoul, Republic of Korea

2. Korea University, Seoul, Seoul, Republic of Korea

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3665314.3670845

Reference10 articles.

1. Newton: A DRAM-maker’s Accelerator-in-Memory (AiM) Architecture for Machine Learning

2. An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices

3. A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations

4. Triple-Skipping Near-MRAM Computing Framework for AIoT Era

5. STT-MRAM Sensing: A Review

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