A Multistep Multistage Fifth-Order Incremental Delta Sigma Analog-to-Digital Converter for Sensor Interfaces
Author:
Affiliation:
1. Department of Electronics and Electrical Engineering, National Yang Ming Chiao Tung University (NYCU), Hsinchu, Taiwan
Funder
National Science and Technology Council, Taiwan
Novatek Microelectronics
Egis Technology
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/10262388/10171806.pdf?arnumber=10171806
Reference41 articles.
1. A second-order high-resolution incremental A/D converter with offset and charge injection compensation
2. A Hybrid Continuous-Time Incremental and SAR Two-Step ADC With 90.5-dB DR Over 1-MHz BW
3. A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8/spl times/ oversampling ratio
4. A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta–Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS
5. Two‐step multi‐stage incremental ADC
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1. Low‐power multibit delta–sigma modulator based on passive and unattenuated summation scheme;International Journal of Circuit Theory and Applications;2024-06-18
2. A 101-dB SFDR 98.5-dB DR 20-kHz BW Continuous Time Incremental Δ∑ ADC with FIR DAC and Robust Reset Timing for Sensor Interfaces;2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA);2024-04-22
3. Oversampling ADC: A Review of Recent Design Trends;IEEE Access;2024
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