Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory-Reference-Cited by-同舟云学术

Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory

Published:2022-04 Issue:4 Volume:57 Page:986-998
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Kim Sung¹^ORCID,Fayazi Morteza¹^ORCID,Daftardar Alhad¹^ORCID,Chen Kuan-Yu¹^ORCID,Tan Jielun²,Pal Subhankar¹^ORCID,Ajayi Tutu¹^ORCID,Xiong Yan³,Mudge Trevor¹,Chakrabarti Chaitali³^ORCID,Blaauw David¹^ORCID,Dreslinski Ronald¹,Kim Hun-Seok¹^ORCID

Affiliation:

1. Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI, USA

2. Qualcomm, San Diego, CA, USA

3. School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ, USA

Funder

U.S. Government

Defense Advanced Research Projects Agency

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9741814/09696304.pdf?arnumber=9696304

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4. 2.2 A 978GOPS/W Flexible Streaming Processor for Real-Time Image Processing Applications in 22nm FDSOI

5. 2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS

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