2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS-Reference-Cited by-同舟云学术

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2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS

Published:2018-06 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE Symposium on VLSI Circuits
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Author:

Anders Mark,Kaul Himanshu,Mathew Sanu,Suresh Vikram,Satpathy Sudhir,Agarwal Amit,Hsu Steven,Krishnamurthy Ram

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8484863/8502213/08502333.pdf?arnumber=8502333

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3. POAS: a framework for exploiting accelerator level parallelism in heterogeneous environments;The Journal of Supercomputing;2024-03-25

4. DAP: A 507-GMACs/J 256-Core Domain Adaptive Processor for Wireless Communication and Linear Algebra Kernels in 12-nm FINFET;IEEE Journal of Solid-State Circuits;2024

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