Author:
Zhang Minjin,Li Huawei,Li Xiaowei
Cited by
4 articles.
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1. Fault-Tolerant Circuits;Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design;2023
2. A High-Precision On-Chip Path Delay Measurement Architecture;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2012-09
3. Path Delay Test Generation Toward Activation of Worst Case Coupling Effects;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2011-11
4. Delay Faults Testing;Design and Test Technology for Dependable Systems-on-Chip