Affiliation:
1. Institute of Informatics of the Slovak Academy of Sciences, Slovakia
Abstract
Embedded digital blocks and their interconnections have to be verified by at-speed testing to satisfy the quality and reliability of nowadays System-on-Chips (SoCs). Once a chip is fabricated, it must be tested for pre-specified clock frequency and therefore testing has also to cover speed related faults as well as stuck-at faults. Claim for delay fault testing grows with new technologies. The importance of researching the delay fault testing grows rapidly and obviously the results are published separately for individual problems. The purpose of the chapter is to give an introduction to testing the timing malfunctions in digital circuits. The classification of existing basic and advanced delay fault models is presented with advantages and limitations. The latest test application techniques are described for scan-based synchronous and asynchronous circuits.
Reference31 articles.
1. Abraham, J., Goel, U., & Kumar, A. (2006). Multi-Cycle Sensitizable Transition Delay Faults. In Proc. VLSI Test Symposium (pp. 306-311).
2. Techniques to Prioritize Paths for Diagnosis. IEEE Transactions on Very Large Scale Integration (VLSI);R.Adapa;Systems,2010
3. Brzozowski, J. A., & Raahemifar, K. (1995). Testing C-elements is not elementary. In International Symposium on Asynchronous Circuits and Systems (pp. 150-159).
4. IEEE Standard 1500 Compatible Delay Test Framework. IEEE Transactions on Very Large Scale Integration (VLSI);P. L.Chen;Systems,2009
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献