A High-Precision On-Chip Path Delay Measurement Architecture-Reference-Cited by-同舟云学术

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A High-Precision On-Chip Path Delay Measurement Architecture

Published:2012-09 Issue:9 Volume:20 Page:1565-1577
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Pei Songwei,Li Huawei,Li Xiaowei

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/6236332/05970107.pdf?arnumber=5970107

Cited by 17 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Novel All-Digital on-Chip Aging Sensor Robust to Process Variations;2022 7th International Conference on Integrated Circuits and Microsystems (ICICM);2022-10-28

2. On-Chip Structures for Fmax Binning and Optimization;Sensors;2022-02-11

3. Low-Process–Voltage–Temperature-Sensitivity Multi-Stage Timing Monitor for System-on-Chip Applications;Electronics;2021-06-30

4. Online Safety Checking for Delay Locked Loops via Embedded Phase Error Monitor;IEEE Transactions on Emerging Topics in Computing;2021-04-01

5. Tiny Phase-Error Monitor for Fault and Soft-Error Tolerant DLL To Support Graceful Degradation and Module-Level Testing;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021

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