Affiliation:
1. VLSI Design and Nano-Scale Computational Lab, PDPM Indian Institute of Information Technology Design and Manufacturing Jabalpur, Jabalpur, India
Funder
PDPM IIITDM Jabalpur, Project title “Design and Performance Investigation of Negative Capacitance Tunnel FET for Digital/Analog Applications,”
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Safety, Risk, Reliability and Quality,Electronic, Optical and Magnetic Materials
Cited by
39 articles.
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