A New Scheme of the Low-Cost Multiple-Node-Upset-Tolerant Latch
Author:
Affiliation:
1. Key Laboratory of Integrated Microsystems, Peking University Shenzhen Graduate School, Shenzhen, China
2. Institute of Microelectronics, Peking University, Beijing, China
Funder
Key-Area Research and Development Program of Guangdong Province
Shenzhen Science and Technology Innovation Committee
TSV 3D Integrated Micro/Nano System Lab
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Safety, Risk, Reliability and Quality,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/7298/9730817/09675822.pdf?arnumber=9675822
Reference23 articles.
1. Upset hardened memory design for submicron CMOS technology
2. Low Power, and Highly Reliable Single Event Upset Immune Latch for Nanoscale CMOS Technologies
3. A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells
4. A Novel Latch Circuit against Single Event Upset
5. Double node charge sharing SEU tolerant latch design
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