High Pressure Deuterium Annealing for Improved Immunity Against Stress-Induced Threshold Voltage Degradation
Author:
Affiliation:
1. School of Electronics Engineering, Chungbuk National University, Cheongju, Republic of Korea
2. School of Electrical Engineering, Korea Advanced Institute of Technology, Daejeon, Republic of Korea
Funder
National Research Foundation of Korea (NRF) Grant
Korea Government
Nano Material Technology Development Program through the National Research Foundation of Korea
Ministry of Science, ICT and Future Planning
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Safety, Risk, Reliability and Quality,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/7298/9876000/09844126.pdf?arnumber=9844126
Reference34 articles.
1. Temperature stress on a thin film transistor with a novel BaZnSnO semiconductor using a solution process
2. Observations on the recovery of hot carrier degradation of hydrogen/deuterium passivated nMOSFETs
3. Quantitative Analysis of Deuterium Annealing Effect on Poly-Si TFTs by Low Frequency Noise and DC ${I}$ – ${V}$ Characterization
4. On the mechanism for interface trap generation in MOS transistors due to channel hot carrier stressing
5. Low thermal budget annealing technique for high performance amorphous In-Ga-ZnO thin film transistors
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1. Low-Temperature Deuterium Annealing for High-Performance and Reliable Poly-Si Channel Thin-Film Transistors;IEEE Transactions on Electron Devices;2024-02
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4. Low-Temperature Deuterium Annealing for the Recovery of Ionizing Radiation-Induced Damage in MOSFETs;IEEE Transactions on Device and Materials Reliability;2023-06
5. Comprehensive Study on Trap-Induced Bias Instability via High-Pressure D 2 and N 2 Annealing;IEEE Transactions on Device and Materials Reliability;2023-06
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