Local Bit-Line SRAM Architecture With Data-Aware Power-Gating Write Assist
Author:
Affiliation:
1. School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea
Funder
National Research Foundation of Korea
Korea Government
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/9996096/09891835.pdf?arnumber=9891835
Reference19 articles.
1. 40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist
2. Demonstration of highly scaled FinFET SRAM cells with high-κ/metal gate and investigation of characteristic variability for the 32 nm node and beyond
3. A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors
4. Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond
5. Low-k interconnect stack with metal-insulator-metal capacitors for 22nm high volume manufacturing
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