Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

Author:

Kawasaki H.,Basker V. S.,Yamashita T.,Lin C.-H.,Zhu Y.,Faltermeier J.,Schmitz S.,Cummings J.,Kanakasabapathy S.,Adhikari H.,Jagannathan H.,Kumar A.,Maitra K.,Wang J.,Yeh C.-C.,Wang C.,Khater M.,Guillorn M.,Fuller N.,Chang J.,Chang L.,Muralidhar R.,Yagishita A.,Miller R.,Ouyang Q.,Zhang Y.,Paruchuri V. K.,Bu H.,Doris B.,Takayanagi M.,Haensch W.,McHerron D.,O'Neill J.,Ishimaru K.

Publisher

IEEE

Cited by 19 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A High-Speed Sense Amplifier Based Flip Flop with a Single Ended Latch Design and Low Voltage Operating Capabilities;2023 3rd International Conference on Smart Generation Computing, Communication and Networking (SMART GENCON);2023-12-29

2. Negative Bias-Temperature Instabilities and Low-Frequency Noise in Ge FinFETs;IEEE Transactions on Device and Materials Reliability;2023-03

3. Local Bit-Line SRAM Architecture With Data-Aware Power-Gating Write Assist;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-01

4. Extremely Scaled Silicon Nanosheet Transistors;2022 IEEE International Conference on Emerging Electronics (ICEE);2022-12-11

5. Evaluation of the Effect of FinFET Structure Parameters on Electrical Characteristics Using TCAD Modeling Tools;Russian Microelectronics;2022-12

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