Demonstration of highly scaled FinFET SRAM cells with high-κ/metal gate and investigation of characteristic variability for the 32 nm node and beyond

Author:

Kawasaki H.,Khater M.,Guillorn M.,Fuller N.,Chang J.,Kanakasabapathy S.,Chang L.,Muralidhar R.,Babich K.,Yang Q.,Ott J.,Klaus D.,Kratschmer E.,Sikorski E.,Miller R.,Viswanathan R.,Zhang Y.,Silverman J.,Ouyang Q.,Yagishita A.,Takayanagi M.,Haensch W.,Ishimaru K.

Publisher

IEEE

Cited by 14 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Suppression of Threshold Voltage Variation by H₂ Plasma Improved KrF Photoresist Profile;IEEE Transactions on Electron Devices;2024-09

2. Local Bit-Line SRAM Architecture With Data-Aware Power-Gating Write Assist;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-01

3. FinFET Optimization in the Design of 6T SRAM Cell;Lecture Notes in Electrical Engineering;2020

4. A novel method for source/drain ion implantation for 20 nm FinFETs and beyond;Journal of Materials Science: Materials in Electronics;2019-04-08

5. Analysis of subthreshold SOI FinFET based two stage OTA for low power;Analog Integrated Circuits and Signal Processing;2018-08-20

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