Analysis of subthreshold SOI FinFET based two stage OTA for low power-Reference-Cited by-同舟云学术

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Analysis of subthreshold SOI FinFET based two stage OTA for low power

Published:2018-08-20 Issue:2 Volume:98 Page:277-289
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Sonkusare Reena,Pilankar Prathamesh Milind,Rathod Surendra S.

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/article/10.1007/s10470-018-1305-3/fulltext.html

Reference31 articles.

1. Poiroux, T., Vinet, M., Faynot, O., Lolivier, J., Ernst, T., Previtali, B., et al. (2005). Multiple gate devices: Advantages and challenges. Micro Electronic Engineering, 80, 378–385. https://doi.org/10.1016/j.mee.2005.04.095 .

2. Subramanian, V., Parvais, B., Borremans, J., Mercha, A., Linten, D., Wambacq, P, Loo, J., Dehan, M., Gustin, C., Collaert, N., Kubicek, S., Lander, R., Hooker, J., Cubaynes, F., Donnay, S., Jurczak, M., Groeseneken, G., Sansen, W., & Decoutere, S. (2006). Planar Bulk MOSFETs versus FinFETs: An Analog/RF Perspective, IEEE Transactions on Electron Devices. https://doi.org/10.1109/TED.2006.885649 .

3. Colinge, J.-P. (2004). Multiple-gate SOI MOSFETs. Solid-State Electronics, 48, 897–905. https://doi.org/10.1016/j.sse.2003.12.020 .

4. Grasso, A. D., Pennisi, S., Scotti, G., & Trifiletti, A. (2017). 0.9-V class-AB Miller OTA in 0.35-m CMOS with threshold-lowered non-tailed differential pair. IEEE Transactions on Circuits and Systems-I Regular Papers. https://doi.org/10.1109/TCSI.2017.2681964 .

5. Grasso, A. D., Marano, D., Palumbo, G., & Pennisi, S. (2015). Design methodology of subthreshold three-stage CMOS OTAs suitable for ultra-low-power low-area and high driving capability. IEEE Transactions on Circuits and Systems-I Regular Papers. https://doi.org/10.1109/TCSI.2015.2411796 .

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