A gigabit multidrop serial backplane for high-speed digital systems based on asymmetrical power splitter-Reference-Cited by-同舟云学术

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A gigabit multidrop serial backplane for high-speed digital systems based on asymmetrical power splitter

Published:2005-01 Issue:1 Volume:52 Page:5-9
ISSN:1057-7130
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Esper-Chain R.,Tobajas F.,Tubio O.,Arteaga R.,de Armas V.,Sarmiento R.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Signal Processing

Link

http://xplorestaging.ieee.org/ielx5/8920/30032/01375050.pdf?arnumber=1375050

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Reflection Self-Canceling Design Technique for Multidrop Memory Interfaces;IEEE Transactions on Components, Packaging and Manufacturing Technology;2022-11

2. Challenges toward the application of high-speed digital signaling to multi-drop transmission system with reflection compensation lines;IEICE Communications Express;2021-03-01

3. Multidrop Transmission System Based on Reflection-Canceling Scheme With Reflection Compensation Lines;IEEE Transactions on Electromagnetic Compatibility;2020-12

4. Parallel Branching of Two 2-DIMM Sections With Write-Direction Impedance Matching for an 8-Drop 6.4-Gb/s SDRAM Interface;IEEE Transactions on Components, Packaging and Manufacturing Technology;2019-02

5. 4-Slot, 8-Drop Impedance-Matched Bidirectional Multidrop DQ Bus With a 4.8-Gb/s Memory Controller Transceiver;IEEE Transactions on Components, Packaging and Manufacturing Technology;2013-05

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