Challenges toward the application of high-speed digital signaling to multi-drop transmission system with reflection compensation lines
Author:
Affiliation:
1. Information R&D Center, Mitsubishi Electric Corp.
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
General Medicine
Link
https://www.jstage.jst.go.jp/article/comex/10/3/10_2020XBL0145/_pdf
Reference6 articles.
1. [1] R. Esper-Chain, F. Tobajas, O. Tubio, R. Arteaga, V. de Armas, and R. Sarmiento, “A gigabit multidrop serial backplane for high-speed digital systems based on asymmetrical power splitter,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 52, no. 1, pp. 5-9, 2005. DOI: 10.1109/TCSII.2004.838661
2. [2] F. Tobajas, R. Esper-Chain, S. Tubio, R. Arteaga, V. de Armas, and R. Sarmiento, “Experimental gigabit multidrop serial backplane for high speed digital systems,” IEEE International Symposium on Circuits and Systems, pp. 3821-3824, 2005. DOI: 10.1109/ISCAS.2005.1465463
3. [3] S. Sayfan-Altman, V. Vulfin, and M. Haridim, “Designing high-speed signal distribution for multi-drop connection using simulations,” IEEE 28th Convention of Electrical & Electronics Engineers in Israel (IEEEI), 2014. DOI: 10.1109/EEEI.2014.7005788
4. [4] V.A. Barber, K. Lee, and H. Obermaier, “A novel high speed multitap bus structure,” IEEE Trans. Adv. Packag., vol. 24, no. 1, pp. 54-59, 2001. DOI: 10.1109/6040.909625
5. [5] W.-Y. Shin, G.-M. Hong, H. Lee, J.-D. Han, K.-S. Park, D.-H. Lim, S. Kim, D. Shim, J.-H. Chun, D.-K. Jeong, and S. Kim, “4-slot, 8-drop impedance-matched bidirectional multidrop DQ bus with a 4.8-Gb/s memory controller transceiver,” IEEE Trans. Compon. Packag. Manuf. Technol., vol. 3, no. 5, pp. 858-869, 2013. DOI: 10.1109/tcpmt.2012.2231727
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