A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs

Author:

Kim Suhwan,Kosonocky Stephen V.,Knebel Daniel R.,Stawiasz Kevin,Papaefthymiou Marios C.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Signal Processing

Cited by 43 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

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2. POWER AND GROUND BOUNCE REDUCTION TECHNIQUES FOR NANOSCALE VLSI SYSTEMS;i-manager's Journal on Circuits and Systems;2021

3. Controlling Mode Transition Noise Occurred at Ground Rail in Data Preserving MTCMOS Shift Register;Recent Advances in Power Electronics and Drives;2020-12-04

4. Design and Simulation of Reliable Low Power CMOS Logic Gates;IETE Journal of Research;2020-12-03

5. A Novel MTCMOS Stacking Approach to Reduce Mode Transition Energy and Leakage Current in CMOS Full Adder Circuit;Control Applications in Modern Power System;2020-11-27

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