POWER AND GROUND BOUNCE REDUCTION TECHNIQUES FOR NANOSCALE VLSI SYSTEMS-Reference-Cited by-同舟云学术

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POWER AND GROUND BOUNCE REDUCTION TECHNIQUES FOR NANOSCALE VLSI SYSTEMS

Published:2021 Issue:2 Volume:9 Page:1
ISSN:2321-7502
Container-title:i-manager's Journal on Circuits and Systems
language:en
Short-container-title:JCIR

Author:

KAVITHA M.,

Publisher

i-manager Publications

Subject

General Engineering

Reference17 articles.

1. Power Gating with Multiple Sleep Modes

2. Unveiling the ISCAS-85 benchmarks: a case study in reverse engineering

3. Jiao, H. (2012). Noise mitigation in low leakage MTCMOS circuits (Doctoral dissertation). The Hong Kong University of Science and Technology, Hong Kong.

4. Dual diode-Vth reduced power gating structure for better leakage reduction

5. Understanding and minimizing ground bounce during mode transition of power gating structures

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