A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%–80% Input Duty Cycle for SDRAMs-Reference-Cited by-同舟云学术

A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%–80% Input Duty Cycle for SDRAMs

Author:

Lim Ji-Hoon,Bae Jun-Hyun,Jang Jaemin,Jung Hae-Kang,Lee Hyunbae,Kim Yongju,Kim Byungsub,Sim Jae-Yoon,Park Hong-June

Funder

Ministry of Science, ICT and Future Planning (MSIP), Korea, under the Information Technology Research Center (ITRC) support program

Institute for Information & communications Technology Promotion (IITP)

National Research Foundation of the MSIP, Korea

IDEC

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

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