A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%–80% Input Duty Cycle for SDRAMs-Reference-Cited by-同舟云学术

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A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%–80% Input Duty Cycle for SDRAMs

Published:2016-02 Issue:2 Volume:63 Page:141-145
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Lim Ji-Hoon,Bae Jun-Hyun,Jang Jaemin,Jung Hae-Kang,Lee Hyunbae,Kim Yongju,Kim Byungsub,Sim Jae-Yoon,Park Hong-June

Funder

Ministry of Science, ICT and Future Planning (MSIP), Korea, under the Information Technology Research Center (ITRC) support program

Institute for Information & communications Technology Promotion (IITP)

National Research Foundation of the MSIP, Korea

IDEC

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/7394206/7202853.pdf?arnumber=7202853

Cited by 23 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A shared TDC-based fast-lock all-digital DLL using a DCC-embedded delay line;Microelectronics Journal;2024-07

2. A 30 kHz - 3 GHz Clock Duty-Cycle Corrector Circuit for CMOS Integrated Digital Electronic Systems;2023 30th International Conference on Mixed Design of Integrated Circuits and System (MIXDES);2023-06-29

3. A Design of a Dual Delay Line DLL with Wide Input Duty Cycle Range;Electronics;2023-06-16

4. Low-Phase-Error Small-Area 4-Phase DLL With a Single-Ended-Differential-Single-Ended Voltage-Controlled Delay Line;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-01

5. Digital Timing Skew Compensation Ciucuit with Adaptive Duty-Cycle Signals;2021 International Conference on Electronic Communications, Internet of Things and Big Data (ICEIB);2021-12-10

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