Digital Timing Skew Compensation Ciucuit with Adaptive Duty-Cycle Signals
Author:
Affiliation:
1. National Kaohsiung University of Science and Technology,Department of Electronic Engineering,Kaohsiung,Taiwan
2. National Chung-Shan Institute of Science and Technology,Information and Communications Research Division,Taoyuan,Taiwan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9686355/9686372/09686406.pdf?arnumber=9686406
Reference15 articles.
1. A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces
2. All-Digital Delay-Locked Loop-based Frequency Multiplier Operating from 4.0 GHz to 5.6 GHz;khan;ICCCE,0
3. A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop
4. An All-Digital Clock Synchronization Buffer With One Cycle Dynamic Synchronizing
5. A Power-Efficient and Fast-Locking Digital Quadrature Clock Generator with Ping-Pong Phase Detection
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