A 30 kHz - 3 GHz Clock Duty-Cycle Corrector Circuit for CMOS Integrated Digital Electronic Systems-Reference-Cited by-同舟云学术

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A 30 kHz - 3 GHz Clock Duty-Cycle Corrector Circuit for CMOS Integrated Digital Electronic Systems

Published:2023-06-29 Issue: Volume: Page:
ISSN:
Container-title:2023 30th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)
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Author:

Di Patrizio Stanchieri Guido¹,De Marcellis Andrea¹,Faccio Marco¹,Palange Elia¹,Aiello Orazio²

Affiliation:

1. Computer Science and Mathematics (DISIM) University of L’Aquila,Dept. of Information Engineering,L’Aquila,Italy

2. Electronics and Telecommunication Engineering and Naval Architecture (DITEN) University of Genoa,Dept. of Electrical,Genoa,Italy

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10203036/10203110/10203264.pdf?arnumber=10203264

Reference23 articles.

1. A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%–80% Input Duty Cycle for SDRAMs

2. A Multi-Range Duty Cycle Correction Circuit for Multi-Standard Transceivers in 7 nm FinFET

3. A Highly Efficient Composite Class-AB–AB Miller Op-Amp With High Gain and Stable From 15 pF Up To Very Large Capacitive Loads

4. A 40–550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm

5. Harmonic‐free and low cost delay‐locked loop with a 20–80% input duty cycle

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1. A 0.4 V 180 nm CMOS Sub-μW Ultra-Compact and Low-Effort Design PWM-Based ADC;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

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