Harmonic‐free and low cost delay‐locked loop with a 20–80% input duty cycle-Reference-Cited by-同舟云学术

Harmonic‐free and low cost delay‐locked loop with a 20–80% input duty cycle

Published:2017-01 Issue:2 Volume:53 Page:70-71
ISSN:0013-5194
Container-title:Electronics Letters
language:en
Short-container-title:Electron. lett.

Author:

Wei Xing¹,Chen Zhujia¹,Li Wei¹,Yang Haigang¹

Affiliation:

1. System on Programmable Chip Research DepartmentInstitution of Electronics, Chinese Academy of SciencesBeijingPeople's Republic of China

Funder

National Natural Science Foundation of China

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2016.3032

Reference5 articles.

1. A 40–550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm

2. Designing a SAR‐based all‐digital delay‐locked loop with constant acquisition cycles using a resettable delay line;Yao C.‐Y.;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,2015

3. A delay locked loop with a feedback edge combiner of duty cycle corrector with a 20%‐80% input‐duty‐cycle for SDRAMs;Lim J.‐H.;IEEE Trans. Circuits Syst. II, Express Briefs,2016

4. An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance

5. A 3.57 Gb/s/pin low jitter all‐digital DLL with dual DCC circuit for GDDR3 DRAM in 54‐nm CMOS technology;Yun W.‐J.;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,2011

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A design framework for rigorous constrained em-driven optimization of miniaturized antennas with circular polarization;Metrology and Measurement Systems;2023-07-26

2. A 30 kHz - 3 GHz Clock Duty-Cycle Corrector Circuit for CMOS Integrated Digital Electronic Systems;2023 30th International Conference on Mixed Design of Integrated Circuits and System (MIXDES);2023-06-29

3. Multi-phases all-digital DLL with multi-input and wide-range delay line;International Journal of Electronics;2020-07-20

4. Integrated design of filtering antenna with high selectivity and improved performance for L-band applications;AEU - International Journal of Electronics and Communications;2018-12

5. Compact Broadband Dual-Polarized Filtering Dipole Antenna With High Selectivity for Base-Station Applications;IEEE Transactions on Antennas and Propagation;2018-11