A 3-8bit Reconfigurable Hybrid ADC Architecture with Successive-approximation and Single-slope Stages for Computing in Memory-Reference-Cited by-同舟云学术

A 3-8bit Reconfigurable Hybrid ADC Architecture with Successive-approximation and Single-slope Stages for Computing in Memory

Published:2022-05-28 Issue: Volume: Page:
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Container-title:2022 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Fan Wuyu¹,Li Yuandong¹,Du Li¹,Li Likai¹,Du Yuan¹

Affiliation:

1. Nanjing University,Nanjing,China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937285.pdf?arnumber=9937285

Reference30 articles.

1. A 280MS/s 12b SAR-Assisted Hybrid ADC with Time Domain Sub-Range Quantizer in 45nm CMOS

2. A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors

3. Robust Processing-In-Memory with Multi-bit ReRAM using Hessian-driven Mixed-Precision Computation;dash;IEEE Transactions on computeraided design of integrated circuits and systems,0

4. MRIMA: An MRAM-Based In-Memory Accelerator

5. Computing-in-Memory Paradigm Based on STT-MRAM with Synergetic Read/Write-Like Modes

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