A Compilation Framework for SRAM Computing-in-Memory Systems With Optimized Weight Mapping and Error Correction-Reference-Cited by-同舟云学术

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A Compilation Framework for SRAM Computing-in-Memory Systems With Optimized Weight Mapping and Error Correction

Published:2024-08 Issue:8 Volume:43 Page:2379-2392
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Bai Yichuan¹^ORCID,Li Yaqing¹^ORCID,Zhang Heng¹^ORCID,Jiang Aojie¹^ORCID,Du Yuan¹^ORCID,Du Li¹^ORCID

Affiliation:

1. School of Electronic Science and Engineering, Nanjing University, Nanjing, China

Funder

National Key Research and Development Program of China

Natural Science Foundation of China

Ministry of Education

Fundamental Research Funds for the Central Universities

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/43/10604458/10436438.pdf?arnumber=10436438

Reference49 articles.

1. An Efficient High-Throughput Structured-Light Depth Engine

2. Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor Into Convolutional Neural Network Accelerators For Low-Power Edge Devices

3. Cellular Logic-in-Memory Arrays

4. A Survey of Convolutional Neural Networks: Analysis, Applications, and Prospects

5. Interpolated finite impulse response filters

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